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ARINC 429 Bus Interface
Product Summary
Intended Use
* * ARINC 429 Transmitter (Tx) ARINC 429 Receiver (Rx) * * -
Core Deliverables
* Evaluation Version - Compiled RTL Simulation Model, Compliant with the Actel Libero(R) Integrated Design Environment (IDE) Structural VHDL and Verilog Netlists VHDL or Verilog Core Source Code Synthesis Scripts
Netlist Version RTL version - -
Key Features
* * * * Supports ARINC Specification 429-16 Configurable up to 16 Rx and 16 Tx Channels Programmable FIFO Depth - - - * - - * * * * Up to 512 Words Rx and Tx Channels independently Up to 64 Words Programmable Interrupt Generation
* *
Verification Testbench - Verilog User Testbenches - - Libero IDE Compatible VHDL and Verilog
Configurable Label Memory Size Rx and Tx Channels independently Up to 256 Words
Development System
* * Complete ARINC 429 Rx/Tx Implementation - - * Implemented in an APA600 Device Controlled Via an External Terminal Using Core8051 and RS232 Links
Internal, Wrap-Around Testing Software Compatible with Legacy Devices Selectable Clock Speed - - - 1, 10, 16, or 20 MHz 12.5 100 kbps Optional 50 kbps Provides Direct CPU Access to Memory Simple Interface to Core8051 EDAC Support with RTAX-S Family Supports Standard Line Drivers and Receivers * Selectable Data Rate on Each Channel
Includes Line Driver and Receiver Components
Synthesis and Simulation Support
* * Directly Supported within the Actel Libero IDE Synthesis: - - - - - Synplicity(R) ExemplarTM Synopsys(R) Vital-Compliant VHDL Simulators OVI-Compliant Verilog Simulators
*
CPU Interface - -
* * *
Memory - - ARINC 429 Bus Interface Available as Integrated Tx and Rx
Simulation
Supported Families
* * * * * Fusion ProASIC(R)3/E ProASICPLUS(R) Axcelerator(R) RTAX-S
Verification and Compliance
* * Actel-Developed Simulation Testbench Core Implemented Development System on the ARINC 429
September 2006 (c) 2006 Actel Corporation
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Contents
General Description .................................................... 2 ARINC 429 Overview .................................................. 2 Core429 Device Requirements ................................... 3 Memory Requirements ............................................... 4 Core429 Overview ...................................................... 5 Default Mode ............................................................. 5 Functional Description ............................................... 5 Legacy Mode ............................................................... 7 Core Parameters ......................................................... 8 I/O Signal Descriptions ............................................... 8 Default Mode Operation ......................................... 10 Legacy Operation ..................................................... 13 Status Register .......................................................... 15 CPU Interface Timing for Default Mode ................. 16 Clock Requirements .................................................. 17 Core429 Verification ................................................ 17 Testbench .................................................................. 17 Line Drivers ............................................................... 18 Line Receivers ........................................................... 18 Loopback Interface ................................................... 18 Development System ................................................ 18 Ordering Information .............................................. 19 List of Changes ......................................................... 20 Datasheet Categories ............................................... 21
Rx I/F
CPU
Glue Logic
CPU Interface
RxHi RxLo TxHi TxLo
Tx I/F
CoreARINC429 Actel FPGA
Figure 1 * Typical Core429 System--One Tx and One Rx
ARINC 429 Overview
ARINC 429 is a two-wire, point-to-point data bus that is application-specific for commercial and transport aircraft. The connection wires are twisted pairs. Words are 32 bits in length and most messages consist of a single data word. The specification defines the electrical standard and data characteristics and protocols. ARINC 429 uses a unidirectional data bus standard (Tx and Rx are on separate ports) known as the Mark 33 Digital Information Transfer System (DITS). Messages are transmitted at 12.5, 50 (optional), or 100 kbps to other system elements that are monitoring the bus messages. The transmitter is always transmitting either 32-bit data words or the Null state. The ARINC standard supports High, Low, and Null states (Figure 2). A minimum of four Null bits should be transmitted between ARINC words. No more than 20 receivers can be connected to a single bus (wire pair) and no less than one receiver, though there will normally be more.
General Description
Core429 provides a complete Transmitter (Tx) and Receiver (Rx). A typical system implementation using Core429 is shown in Figure 1. The core consists of three main blocks: Transmit, Receive, and CPU Interface (Figure 1). Core429 requires connection to an external CPU. The CPU interface configures the transmit and receive control registers and initializes the label memory. The core interfaces to the ARINC 429 bus through an external ARINC 429 line driver and line receiver. A detailed description of the Rx interface and Tx interface is provided in the "Functional Description" section on page 5.
1 High +5 A Null 0 Low -5 High +5 B Null 0 Low -5 1
2
3
4
5
6
7
8
9 10
32 Bit Number "A" Leg "B" Leg
0
1
1
0
1
0
1
0
0
1
Data
Figure 2 *
ARINC Standard
External Components
There are two external components required for proper operation of Core429: * * Standard ARINC 429 line driver Standard ARINC 429 line receiver
Figure 3 on page 3 shows the bit positions of ARINC data. Each ARINC word contains five fields: * Parity
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* * * *
Sign/Status Matrix Data Source/Destination Identifiers Label
receiver the data is intended. Bits 1 to 8 contain a label (label words) identifying the data type. Label words are quite specific in ARINC 429. Each aircraft may be equipped with different electronic equipment and systems needing interconnection. A large amount of equipment may be involved, depending on the aircraft. The ARINC specification identifies the equipment ID, a series of digital identification numbers. Examples of equipment are Flight Management Computers, Inertial Reference Systems, Fuel Tanks, Tire Pressure Monitoring Systems, and GPS Sensors.
The parity bit is bit 32 (the MSB). SSM is the Sign/Status Matrix and is included as bits 30 and 31. Bits 11 to 29 contain the data. Binary Coded Decimal (BCD) and binary encoding (BNR) are common ARINC data formats. Data formats can also be mixed. Bits 9 and 10 are Source/ Destination Identifiers (SDI) and indicate for which
32 P
31 SSM
30
29 DATA MSB PAD
11 DISCRETES LSB
10 SDI
9
8 LABEL
1
Figure 3 *
ARINC Data Bit Positions
Transmission Order
The least significant bit of each byte, except the label, is transmitted first, and the label is transmitted ahead of the data in each case. The order of the bits transmitted on the ARINC bus is as follows: 8, 7, 6, 5, 4, 3, 2, 1, 9, 10, 11, 12, 13 ... 32.
Core429 Device Requirements
Core429 can be implemented in several Actel FPGA devices. Table 1 through Table 5 on page 4 provide typical utilization figures using standard synthesis tools for different Core429 configurations. Table 1 assumes that the label size is set to 64 and FIFO depth is set to 64.
Table 1 * Device Utilization for One Tx Module Cells or Tiles Family Fusion ProASIC3/E ProASICPLUS Axcelerator RTAX-S Table 2 * Combinatorial 363 363 441 212 258 Sequential 147 147 146 145 171 Total 510 510 587 357 429 Memory Blocks 1 1 1 1 1 Device AFS600 A3PE600 APA075 AX125 RTAX250S Utilization 4% 4% 19% 18% 10%
Device Utilization for One Rx Module Cells or Tiles
Family Fusion ProASIC3/E ProASICPLUS Axcelerator RTAX-S
Combinatorial 431 431 588 307 350
Sequential 233 233 236 234 259
Total 664 664 824 541 609
Memory Blocks 2 2 2 2 2
Devices AFS600 A3PE600 APA075 AX125 RTAX250S
Utilization 5% 5% 27% 27% 14%
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Table 3 *
Device Utilization for One Rx and One Tx Module Cells or Tiles
Family Fusion ProASIC3/E ProASICPLUS Axcelerator RTAX-S Table 4 *
Combinatorial 848 848 1,084 518 604
Sequential 609 609 377 378 429
Total 1,457 1,457 1,461 896 1,033
Memory Blocks 3 3 3 3 3
Device AFS600 A3PE600 APA075 AX125 RTAX250S
Utilization 10% 10% 48% 44% 24%
Device Utilization for 16 Rx and 16 Tx Modules Cells or Tiles
Family Fusion ProASIC3/E ProASICPLUS Axcelerator RTAX-S Table 5 *
Combinatorial 13,435 13,435 16,835 8,044 9,594
Sequential 9,614 9,614 5,928 5,944 6,745
Total 23,049 23,049 22,763 13,988 16,339
Memory Blocks 48 48 48 48 48
Device AFS1500 A3PE1500 APA750 AX2000 RTAX2000S
Utilization 60% 60% 69% 43% 51%
Device Utilization for Legacy Mode (2 Rx and 1 Tx) Cells or Tiles Memory Blocks 5 5 5 5 5
Family Fusion ProASIC3/E ProASICPLUS Axcelerator RTAX-S
Combinational 1,444 1,444 1,840 955 1,062
Sequential 1,068 1,068 674 653 729
Total 2,512 2,512 2,514 1,608 1,791
Device AFS600 A3PE600 APA150 RTAX250S RTAX250S
Utilization 18% 18% 41% 20% 42%
Core429 clock rate can be programmed to be 1, 10, 16, or 20 MHz. All the Actel families listed above easily meet the required performance. Core429 I/O requirements depend on the system requirements and the external interfaces. If the core and memory blocks are implemented within the FPGA and the CPU interface has a bidirectional data bus, then
approximately 74 I/O pins are required to implement four Rx and four Tx modules. The core will require 62 pins to implement one Rx and one Tx module. The core has various FIFO flags available for debugging purposes. These flags may not be needed in the final design and this will reduce the I/O count.
Memory Requirements
The number of memory blocks required differs, depending on whether each channel is configured the same or differently.
Each Channel Configured the Same
Use EQ 1 to calculate the number of memory blocks required if each channel is configured the same. Number of memory blocks = NRx * (INT (LABEL_SIZE/X) + INT (RX_FIFO_DEPTH/Y) + NTx * INT (FIFO_DEPTH/Y),
EQ 1
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where NRx is the number of receive channels, NTx is the number of transmit channels, INT is the function to round up to the next integer, and X and Y are defined in Table 6.
Each Channel Configured Differently
Use EQ 2 to calculate the number of memory blocks required if each channel is configured differently.
NTx - 1 NRx - 1
Number of memory blocks =
I=0
INT(FIFO_DEPTH[I]/Y +
I=0
(INT(LABEL_SIZE[I]/X) + INT(FIFO_DEPTH[I]/Y)),
EQ 2
where NRx is the number of receive channels, NTx is the number of transmit channels, INT is the function to round up to the next integer, and X and Y are defined in Table 6.
Table 6 * Memory Parameters X 512 512 256 512 Y 128 128 64 128
Device Family Fusion ProASIC3/E ProASIC
PLUS
Axcelerator/RTAX-S
Examples for the ProASIC3/E Device Family
If the design has 2 receivers, 1 transmitter, 64 labels for each receiver, 32-words-deep FIFO for each receiver and transmitter, then the number of memory blocks = 2 * (INT (64/512) + INT (32/128)) + 1 * INT (32/128) = 2 * (1 + 1) + 1 * (1) = 5. If the design has 2 receivers, 1 transmitter, 32 labels for receiver # 1, 64 labels for receiver # 2, 32 words-deep FIFO for receiver # 1, 64-words-deep FIFO for receiver # 2, and 64-words-deep FIFO for transmitter, then the number of memory blocks = INT (64/128) + (INT (32/512) + INT (32/128)) + (INT (64/512) + INT (64/128)) = 1 + (1 + 1) + (1 + 1) = 5.
Core429 Overview
Core429 provides a complete and flexible interface to a microprocessor and an ARINC 429 data bus. Connection to an ARINC 429 data bus requires additional line drivers and line receivers. Core429 interfaces to a processor through the internal memory of the receiver. Core429 can be easily interfaced to an 8-, 16- or 32-bit data bus. Look-up tables loaded into memory enable the Core429 receive circuitry to filter and sort incoming data by label and destination bits. Core429 supports multiple (configurable) ARINC 429 receiver channels, and each receives data independently. The receiver data rates (high or low speed) can be programmed independently. Core429 can decode and sort data based on the ARINC 429 Label and SDI bits and stores it in FIFO. Each receiver uses programmable FIFO to buffer received data. Core429 supports multiple
(configurable) ARINC 429 transmit channels and each channel can transmit data independently.
Default Mode
This is the recommended mode and allows the user to configure the core with user-defined transmit and receive channels.
Functional Description
The core has three main blocks: Transmit, Receive, and CPU interface. The core can be configured to provide up to 16 transmit and receive channels.
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Figure 4 gives a functional description of the Rx block.
RxHi RxLo
Data Sync and Clock Recovery
32-Bit Shift Register Bit Counter Word Gap Timer Compare Label Label Memory
clk cpu_add cpu_wen cpu_ren cpu_din cpu_dout cpu_wait CPU I/F
Parity Check Control Logic Control Reg Status Reg
FIFO
Figure 4 *
Core429 Rx Block Diagram
The Rx block is responsible for recovering the clock from the input serial data and performs serial-to-parallel conversion and gap/parity check on the incoming data. It also interfaces with the CPU. The Rx module contains two 8-bit registers. One is used for control function and the other is used for status. Refer to Table 14 on page 11 and Table 15 on page 11 for detailed descriptions of the control and status register bits. The CPU interface configures the internal RAM with the labels, which are used to compare against the incoming labels from the received ARINC data. If the label-compare bit in the receive control register is enabled, then the data which matches its labels with the stored labels will be stored in the FIFO. If the labelcompare bit in the receive control register is disabled, then the incoming data will be stored in the FIFO without comparing against the labels in RAM.
The core supports reloading label memory using bit 7 of the Rx control register. Note that when you set bit 7 to initialize the label memory, the old label content still exists, but the core keeps track only of the new label and does not use the old label during label compare. The FIFO asserts three status signals: * * * rx_fifo_empty: FIFO is empty rx_fifo_half_full: FIFO is filled programmed RX_FIFO_LEVEL rx_fifo_full: FIFO is full up to the
Depending on the FIFO status signals, the CPU will either read the FIFO before it overflows, or not attempt to read the FIFO if it is empty. The interrupt signal int_out_rx is generated when one of the FIFO status signals (rx_fifo_empty, rx_fifo_half_full, and rx_fifo_full) are high.
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Figure 5 gives a functional description of the Tx block.
FIFO
RxHi
32-Bit Parallelto-Serial Register
Waveform Shaper
RxLo
Load clk cpu_add cpu_wen cpu_ren cpu_din cpu_dout cpu_wait CPU I/F
Shift
Parity Generator
Control Logic
Control Reg
Status Reg
Figure 5 *
Core429 Tx Block Diagram
The Tx module converts the 32-bit parallel data from the TX FIFO to serial data. It also inserts the parity bit into the ARINC data when parity is enabled. The CPU interface is used to fill the FIFO with ARINC data. The TX FIFO can hold up to 512 ARINC words of data. The transmission starts as soon as one complete ARINC word has been stored in the transmit FIFO. The Tx module contains two 8-bit registers. One is used for a control function and the other is used for status. The CPU interface allows the system CPU to access the control and status registers within the core. The TX FIFO asserts three status signals: * * * tx_fifo_empty: TX FIFO is empty tx_fifo_half_full: TX FIFO is filled up to the programmed TX_FIFO_LEVEL tx_fifo_full: TX FIFO is full
Depending on the FIFO status signals, the CPU will either read the FIFO before it overflows, or not attempt to read the FIFO if it is empty. The interrupt signal int_out_tx is generated when one of the FIFO status signals (tx_fifo_empty, tx_fifo_half_full and tx_fifo_full) are high.
Legacy Mode
In this mode, there is a legacy interface block that communicates with the CPU interface. When legacy mode is enabled, the core supports two receive (Rx) channels and one transmit (Tx) channel only. This is not configurable.
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Core Parameters
Core429 has several top-level Verilog parameters (VHDL generics) that are used to select the number of channels and FIFO sizes of the core that is implemented. Using these parameters allows the size of the core to be reduced when all the channels are not required.
Table 7 * CLK_FREQ CPU_DATA_WIDTH RXN TXN LEGACY_MODE LABEL_SIZE_i RX_FIFO_DEPTH_j RX_FIFO_LEVEL_k TX_FIFO_DEPTH_l TX_FIFO_LEVEL_m TXRXSPEED_n FIFO and Label Parameters Description Clock Frequency CPU Data Bus Width Rx Channels Tx Channels 0 = Normal mode; 1 = Legacy mode Number of Labels for Rx Channel i Depth of FIFO for Rx Channel j ARINC word FIFO Level for Rx Channel k Depth of FIFO for Tx Channel l ARINC word FIFO Level for Tx Channel m
For RTL versions, the parameters in Table 7 can be directly set. For netlist versions of the core, a netlist implementing four Tx and four Rx channels is provided as per the defaults above. Actel will supply netlists with alternative parameter settings on request.
Parameter Name
Allowed Values 1, 10, 16, 20 MHz 8, 16, 32 bits 1 to 16 1 to 16 0,1 1 to 256 32, 64, 128, 256, 512 1 to 64 32, 64, 128, 256, 512 1 to 64
Default 1 MHz 8 4 4 0 64 32 16 32 16 0
When this parameter is set to '1', a bit rate of 100/50 kbps is 0, 1 selected. Otherwise selects a bit rate of 100/12.5 kbps. The bit rate can be changed for the Rx/Tx channel pair. Refer to the Tx and Rx control register bit descriptions in Table 14 on page 11 and Table 18 on page 12.
Note: Where i, j, k, l, m, and n are from 0 to 15.
I/O Signal Descriptions
ARINC Interface
Table 8 * Name clk reset_n txa [TXN-1:0] txb [TXN-1:0] rxa [RXN-1:0] rxb [RXN-1:0] Clock and Reset Type In In Out Out In In Description Master clock input (1, 10, 16, or 20 Mhz) Active low asynchronous reset ARINC transmit output A ARINC transmit output B ARINC receiver input A ARINC receiver input B
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Default Mode Signals
Table 9 * Name int_out_rx[RXN-1:0] Core Interface Signals Type Out Description Interrupt from each receive channel. This interrupt is generated when one of the following conditions occur: * * * int_out_tx[TXN-1:0] Out FIFO Empty FIFO Full FIFO is full up to the programmed RX_FIFO_LEVEL
This is an active high signal. Interrupt from each transmit channel. This interrupt is generated when one of the following conditions occur: * * * rx_fifo_full[RXN-1:0] rx_fifo_half_full[RXN-1:0] rx_fifo_empty[RXN-1:0] tx_fifo_full[TXN-1:0] tx_fifo_half_full[TXN-1:0] tx_fifo_empty[TXN-1:0] Out Out Out Out Out Out FIFO Empty FIFO Full FIFO is full up to the programmed TX_FIFO_LEVEL
This is an active high signal. RX FIFO full flag for each receive channel. This is an active high signal. RX FIFO programmed level flag for each receive channel. By default it is programmed to half full. This is an active high signal. RX FIFO empty flag for each receive channel.This is an active high signal. TX FIFO full flag for each transmit channel. This is an active high signal. TX FIFO programmed level flag for each transmit channel. By default it is programmed to half full. This is an active high signal. TX FIFO empty flag for each transmit channel. This is an active high signal.
CPU Interface
The CPU interface allows access to the Core429 internal registers, FIFO, and internal memory. This interface is synchronous to the clock.
Table 10 * Name cpu_ren cpu_wen cpu_add [8:0] cpu_din [CPU_DATA_WIDTH-1:0] cpu_dout [CPU_DATA_WIDTH-1:0] int_out cpu_wait CPU Interface Signals Type In In In In Out Out Out Description CPU read enable, active low CPU write enable, active low CPU address CPU data input CPU data output Interrupt to CPU, active high. int_out is the OR function of int_out_rx and int_out_tx. Indicates that the CPU should hold cpu_ren or cpu_wen active while the core completes the read or write operation.
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Legacy Interface
The Legacy interface allows access to the Core429 internal registers, FIFO, and internal memory. This interface is synchronous to the clock. The Tx module contains two 8-bit registers. One is used for control function and the other is used for status.
Table 11 * Name data_ready1 fifo_full1 half_full1 data_ready2 fifo_full2 half_full2 transmit_fifo_full transmit_half_full rsel ctrl_n str_n entx txr pl1_n pl2_n en1_n en2_n test dout data_valid Legacy Interface Signals Type Out Out Out Out Out Out Out Out In In In In Out In In In In In In/Out Out Description Receiver 1 data ready (FIFO not empty) flag Receiver 1 FIFO full Receiver 1 FIFO half full Receiver 2 data ready (FIFO not empty) flag Receiver 2 FIFO full Receiver 2 FIFO half full Transmit FIFO full Transmit FIFO half full Receiver data half word selection Clock for control word register Read status register if rsel = 0, read control register if rsel = 1 Enable transmission Transmitter ready flag. Goes low when ARINC word loaded into FIFO. Goes high after transmission and FIFO empty. Latch enable for word 1 entered from data bus to transmitter FIFO Latch enable for word 2 entered from data bus to transmitter FIFO. Must follow pl1_n. Data Bus control, enables receiver 1 data to outputs Data Bus control, enables receiver 2 data to outputs if en1_n is high Disable transmitter output if high Bidirectional data bus Data is valid when data_valid = 1
Default Mode Operation
In the default mode, the core operates with the following register map.
CPU Address Map
The address bits 0 and 1 are used to create byte indexes.
For an 8-Bit CPU Data Bus:
00 - Byte 0 01 - Byte 1 10 - Byte 2 11 - Byte 3
For a 16-Bit CPU Data Bus:
00 - Lower half word 10 - Upper half word
For 32-Bit CPU Data Bus:
00 - Word The address bits 2 and 3 select the registers within each Rx or Tx block (see "Address Map" on page 11).
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The address bit 4 is used to determine Rx/Tx as follows: 0 - Rx 1 - Tx The address bits 5, 6, 7, and 8 are used for decoding the 16 channels as follows: 0000 - Channel0
Table 12 * CPU Address Bit Positions Channel Number 8 MSB 7 6 5 Tx/Rx 4
0001 - Channel1 . . . .
1110 - Channel14 1111 - Channel15 Table 12 shows the CPU address bit information.
Register Index 3 2 1
Byte Index 0 LSB
9-Bit CPU Address
Register Definitions
Rx Registers
Following is the detailed definition of cpu_add [3:2] decoding and the explanation of Data Register, Control Register, Status Register, and Label Memory Register (Table 13 through Table 16 on page 12).
Table 13 * Bit 31:0 Table 14 * Bit 0 1 2 3 4 Rx Data Register Function Data Rx Control Register Function Data rate Label recognition Enable 32nd bit as parity Reset State 0 0 0 0 0 Type R/W R/W R/W R/W R/W Reset State 0
Address Map 00 - Data Register 01 - Control Register 10 - Status Register 11 - Label Memory
Type R
Description Read Data
Description Data rate: 0 = 100Kb/s; 1 = 12.5 or 50 Kbps Label compare: 0 = disable; 1 = enable 0 = 32nd bit is data; 1 = 32nd bit is parity Parity: 0 = odd; 1 = even 0: SDI bit comparison disabled; 1: SDI bit comparison enabled; ARINC bits 9 and 10 must match bits 5 and 6 respectively.
Parity Decoder
5 6 7
Match header bit 9 Match header bit 10 Reload label memory
0 0 0
R/W R/W R/W
If bit 4 is set then this bit should match the ARINC header bit 9 (SDI bit). If bit 4 is set then this bit should match the ARINC header bit 10 (SDI bit). When bit 7 is set to '1', label memory address pointers are initialized to '000'. Set this bit to change the contents of the label memory.
Table 15 * Bit 0 1 2
Rx Status Register Function FIFO empty FIFO half full or programmed level FIFO full Reset State 0 0 0 Type R R R Description 0 = not empty; 1 = empty 0 = Less than programmed level; 1 = FIFO is filled at least up to programmed level 0 = not full; 1 = full
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Table 16 * Bit 7:0
Rx Label Memory Register Function Label Reset State 0 Type R/W Read/Write Labels Description
Tx Registers
Following is a detailed definition of cpu_add [3:2] decoding and an explanation of the Data Register, Pattern RAM, Control Register, and Status Register.
Address Map 00 - Data Register 01 - Control Register 10 - Status Register 11 - Unused
Table 17 * Bit 31:0 Table 18 * Bit 0 1 2 3 Table 19 * Bit 0 1 2
Tx Data Register Function Data Tx Control Register Function Data rate Loopback Enable 32nd bit as parity Reset State 0 0 0 0 Type R/W R/W R/W R/W Description Data rate: 0 = 100Kb/s; 1 = 12.5 or 50 Kbps 0 = Disable loopback; 1 = Enable loopback 0 = 32nd bit is data; 1 = 32nd bit is parity Parity: 0 = odd; 1 = even Reset State 0 Type W Description Write Data
Parity Tx Status Register Function FIFO empty FIFO half full or programmed level FIFO full
Reset State 0 0 0
Type R R R
Description 0 = not empty; 1 = empty 0 = Less than half full or programmed level; 1 = Half full or programmed level 0 = not full; 1 = full
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Label Memory Operation
The label memory is implemented using an internal memory block. The read address and write address are generated by internal counters. The read and write address counters can be reset by setting bit 7 of the
receive (Rx) control register to '1'. The write counter increments each time the label memory register is written. The read counter increments every time the label memory register is read. The label memory operation is shown in Figure 6.
Number of Active Labels +1 Read Enable Reset Label Memory Block RDATA WADDR +1 Write Address Counter Write Enable Reset Rx Control Register Bit Label Enable Read Data (Rx Label Memory Register) Read Address Counter RADDR WDATA Write Data (Rx Label Memory Register)
Rx Control Register Bit
Figure 6 *
Label Memory Diagram
To program labels, the CPU first resets the read and write counters by setting bit 7 of the receive (Rx) control register to '1'. Then the labels are written to the label memory. The core will compare the incoming ARINC word label (bit 1 to 8 of ARINC word) against the labels contained in the label memory. The contents of the label memory can be read by reading the label memory register. While writing to or reading from label memory,
bit 1 of the receive (Rx) control register should be set to '0'. To reload the label memory, set bit 7 of the receive (Rx) control register to '1'. The core will then ignore all previous labels and new labels can be written to the label memory.
Legacy Operation
In this mode, there is a legacy interface block that communicates with the CPU interface. When legacy mode is enabled, the core supports two receive (Rx) channels and one transmit (Tx) channel only. Legacy mode is not configurable to support multiple transmit and receive channels. The purpose of the legacy mode interface is to replace existing standard products.
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Control Register
Core429 contains a 16-bit control register, which is used to configure the Rx and Tx channels. The control register bits 0 to 15 are loaded from the databus when CTRL_n is low. The control register contents are output on the databus when RSEL is high and STR_n is low. Each bit of the control register description is explained in Table 20.
Table 20 * Bit 0 1 Legacy Control Register Function Receiver 1 data rate Label compare Reset State Type 0 0 R/W R/W Description Data rate: 0 = 100 kbps; 1 = 12.5 kbps. Note: Does not support 50 kbps. 0 = disable; 1 = enable Load 16 labels using pl1_n/pl2_n Read 16 labels using en1_n/en2_n 0: Disable label recognition 1: Enable label recognition 0: Disable label recognition 1: Enable label recognition 0 = 32 bit is data; 1 = 32 bit is parity 0: The transmitter's digital outputs are internally connected to the receiver logic inputs. 1: Normal operation 0: Receiver 1 decoder disabled 1: ARINC bits 9 and 10 must match bits 7 and 8 of the control register. If receiver 1 decoder is enabled, the ARINC bit 9 should match this bit. If receiver 1 decoder is enabled, the ARINC bit 10 should match this bit. 0: Receiver 2 decoder disabled 1: ARINC bits 9 and 10 must match bits 10 and 11 of the control register. If receiver 2 decoder is enabled, the ARINC bit 9 should match this bit. If receiver 2 decoder is enabled, the ARINC bit 10 should match this bit. Parity: 0 = odd; 1 = even Data rate: 0 = 100 kbps; 1 = 12.5 kbps. Note: Does not support 50 kbps. Data rate: 0 = 100 kbps; 1 = 12.5 kbps. Note: Does not support 50 kbps.
2 3 4 5
Enable label recognition (Receiver 1) Enable label recognition (Receiver 2) Enable 32 bit as parity Self test
0 0 0 1
R/W R/W R/W R/W
6 7 8 9 10 11 12 13 14
Receiver 1 decoder Match ARINC bit 9 (receiver 1) Match ARINC bit 10 (receiver 1) Receiver 2 decoder Match ARINC bit 9 (receiver 2) Match ARINC bit 10 (receiver 2) Transmitter parity Transmitter data rate Receiver 2 data rate
0 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
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Status Register
Core429 contains a 16-bit status register which can be read to determine the status of the ARINC receivers, data FIFOs, and transmitter. The contents of the status register are output on the databus when RSEL is low and STR is low. Each bit of the control register description is explained in Table 21.
Table 21 * Bit 0 1 2 3 Legacy Status Register Function Receiver 1 FIFO Empty Receiver 1 FIFO Half Full Receiver 1 FIFO Full Receiver 2 FIFO Empty Receiver 2 FIFO Half Full Receiver 2 FIFO Full Transmitter FIFO Empty Transmitter FIFO Full Transmitter FIFO Half Full Reset State 0 0 0 0 0 0 0 0 0 Type R R R R R R R R R Description 0 = Receiver 1 FIFO not empty 1 = Receiver 1 FIFO empty 0 = Receiver 1 FIFO not half full 1 = Receiver 1 FIFO half full 0 = Receiver 1 FIFO not full 1 = Receiver 1 FIFO full 0 = Receiver 2 FIFO not empty 1 = Receiver 2 FIFO empty 0 = Receiver 2 FIFO not half full 1 = Receiver 2 FIFO half full 0 = Receiver 2 FIFO not full 1 = Receiver 2 FIFO full 0 = Transmitter FIFO not empty 1 = Transmitter FIFO empty 0 = Transmitter FIFO not full 1 = Transmitter FIFO full 0 = Transmitter FIFO not half full 1 = Transmitter FIFO half full
4 5 6 7 8
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ARINC 429 Bus Interface
CPU Interface Timing for Default Mode
The CPU interface signals are synchronized to the Core429 master clock. Figure 7 through Figure 12 on page 17 show the waveforms for the CPU interface.
clk cpu_ren cpu_add[8:0] cpu_dout[31:0] cpu_wait A DDR Data
Note: cpu_ren should be deasserted on the next clock cycle after cpu_wait is deasserted. The read data is available one cycle after cpu_ren is sampled. Figure 7 * CPU Interface Control/Status Register Read Cycle
Write Done clk cpu_wen cpu_add[8:0] cpu_din[31:0] cpu_wait A DDR
Note: cpu_wen should be deasserted on the next clock cycle after cpu_wait is deasserted. The write is done two cycles after cpu_wen is sampled. Figure 8 * CPU Interface Control Register Write Cycle
clk cpu_ren cpu_add[8:0] cpu_dout[31:0] cpu_wait A DDR Data
Note: cpu_ren should be deasserted on the next clock cycle after cpu_wait is deasserted. The read data is available six cycles after cpu_ren is sampled. Figure 9 * CPU Interface Data Register Read Cycle
Write clk cpu_wen cpu_add[8:0] cpu_din[31:0] cpu_wait A DDR Data
cpu_wen should be deasserted on the next clock cycle after cpu_wait is deasserted. The write is done two cycles after cpu_wen is sampled. Figure 10 * CPU Interface Data Register Write Cycle
Note:
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ARINC 429 Bus Interface
clk cpu_ren cpu_add[8:0] cpu_dout cpu_wait Data
cpu_ren should be deasserted on the next clock cycle after cpu_wait is deasserted. The read data is available six cycles after cpu_ren is sampled. Figure 11 * CPU Interface Label Memory Read Cycle
Note:
Write clk cpu_wen cpu_add[8:0] cpu_din[31:0] cpu_wait A DDR Data
Note: cpu_wen should be deasserted on the next clock cycle after cpu_wait is deasserted. The write is done two cycles after cpu_wen is sampled. Figure 12 * CPU Interface Label Memory Write Cycle
Clock Requirements
To meet the ARINC 429 transmission bit rate requirements, the Core429 clock input must be 1, 10, 16, or 20 MHz with a tolerance of 0.01%.
sent to the receiver. The CPU model can retrieve the receive data through the CPU interface and compare it against the transmitted data. The core comes with three testbenches: a full verification testbench that demonstrates full operation in Verilog, and two user testbenches, one in VHDL and the other in Verilog. The user testbenches are intended to simplify core integration into the target system (Figure 13). This consists of the core connections to a CPU model and loopback logic that connects Tx output to the Rx input.
Core429 Verification
The comprehensive verification simulation testbench (included with the Netlist and RTL versions of the core) verifies correct operation of the Core429 macro. The verification testbench applies several tests to the Core429 macro, including: * * * * * Receive Interface tests Transmit Interface tests CPU Interface tests Legacy Interface tests Loopback tests
Core429
Rx I/F0 Tx I/F0
RxH0 RxL0 TxH0 TxL0
CPU Model
CPU I/F
Using the supplied user testbench as a guide, the user can easily customize the verification of the core by adding or removing tests.
Loopback I/F RXH3 RxL3 TxH3 TxL3
Rx I/F3 Tx I/F3
Testbench
The CPU model sets up Core429 via the CPU interface and loads the transmit data. The transmit data will be
Figure 13 * Testbench Diagram
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ARINC 429 Bus Interface
Line Drivers
Core429 needs ARINC 429 line drivers to drive the ARINC 429 data bus. Core429 is designed to directly interface to common ARINC 429 line drivers, such as the HOLT HI-8382/HI-8383, DDC DD-03182 or Device Engineering DEI1070. Figure 14 shows the connections required from Core429 to the line drivers.
Line Driver RxHi RxLo TxHi TxLo
Tx I/F CPU Interface Rx I/F
CoreARINC429
Line Receiver
Figure 14 *
Core429 Line Driver and Line Receiver Interface
Line Receivers
Core429 needs ARINC 429 line receivers to receive the ARINC 429 data bus. Core429 is designed to directly interface to common ARINC 429 line receivers, such as the HOLT HI-8588 or Device Engineering DEI3283. When using ProASICPLUS, RTAX-S, or Axcelerator FPGA families, level translators are required to connect the 5 V output levels of the Core429 line receivers to the 3.3 V input levels of the FPGA. Figure 15 on page 19 shows the connections required from Core429 to the line receivers.
* *
Connect transmit channel 0 output to receive channel 2 input. Connect transmit channel 0 output to receive channel 3 input.
Development System
A complete ARINC 429 development system is also available, Actel part number "Core429-DEV-KIT". The development system uses an external terminal (PC) using a serial UART link to control Core429 with four Rx and four Tx channels implemented in a single ProASICPLUS APA600 FPGA. The loopback interface logic allows the ARINC core to operate with the loopback mode. The development kit (Figure 15 on page 19) includes ARINC line drivers and line receivers. On power-up, Core8051 will read the message from the ADC, which could be the aircraft fuel level or flap position, for example, and transmits over the transmit channel. The message will be transmitted to the receiver through the loopback interface. Then the message will be retrieved by Core8051 from the receiver and displayed on the LCD display. Another way is to transmit the ADC message over the transmit channel through the line drivers to another system similar to the one described above. The message will go through the receive channel of the second system and can be displayed on the LCD display.
Loopback Interface
If the loopback bit in the transmit control register is enabled, the transmit outputs will be connected to the receive inputs. If there are equal numbers of transmit and receive channels, each transmit channel output is connected to the corresponding receive channel input. As an example, transmit channel 0 output is connected to receive channel 0 input. If there are more receive channels than transmit channels, then the extra receive channels are connected to transmit channel 0. As an example, if we have two transmit channels (0 and 1) and four receive channels (0, 1, 2, and 3) then the connections are made as follows: * * Connect transmit channel 0 output to receive channel 0 inputs. Connect transmit channel 1 output to receive channel 1 input.
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ARINC 429 Bus Interface
APA600 FPGA Core 8051
Tx1H Tx1L Rx1H Rx1L Tx2H Tx2L Rx2H Rx2L Tx3H Tx3L Rx3H Rx3L Tx4H Tx4L Rx4H Rx4L
Core 429 4Tx and 4Tx UART RS232
Loopback I/F
Terminal
Keypad and LCD DIsplay
ADC
Figure 15 *
Typical Core429 System Diagram
Ordering Information
Core429 can be ordered through your local Actel sales representative. It should be ordered using the following part number: Core429-XX, where XX is the appropriate value from Table 22:
Table 22 * XX EV SN AN SR AR UR Evaluation Version Netlist for single use on Actel devices Netlist for unlimited use on Actel devices RTL for single use on Actel devices RTL for unlimited use on Actel devices RTL for use not restricted to Actel devices Ordering Codes Description
The Evaluation board can also be ordered using the part number "Core429-DEV-KIT".
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ARINC 429 Bus Interface
List of Changes
The following table lists critical changes that were made in the current version of the document.
Previous Version Changes in Current Version (v 5 .0 ) v4.1 The "Key Features" section was updated to modify the selectable data rate on each channel. Figure 2 was added. The "General Description" section and "ARINC 429 Overview" section were updated. A paragraph was added to the end of the "Core429 Device Requirements" section. Table 6 was updated to add Fusion. Figure 3 was updated. The "Default Mode" section was added. The "Functional Description" section was updated. The "Legacy Mode" section was added. Table 7 was updated to add the TXRXSPEED_n parameter, and the table note was updated. The first four rows of Table 9 were moved to Table 8. Table 9 was updated to remove the tx_en signal, modify the int_out_tx signal description, and add the rx_fifo_full through tx_fifo_empty signals. The "Clock and Reset" section was renamed to "ARINC Interface" and the "ARINC Interface" section was renamed to "Default Mode Signals". Table 11 was moved to a later position in the document, just before the "Default Mode" section. Information about the Tx module was added to the "Legacy Interface" section. The channel decoding values were updated for the 32-bit CPU data bus in the "Default Mode Operation" section. The Address Map was updated in the "Rx Registers" section and the "Tx Registers" section. Table 14 was updated to modify the data rate, decoder, match header bit 9, and match header bit 10 descriptions. Label memory address was renamed reload label memory, and its description was updated. Table 15 was updated to rename FIFO half full to FIFO half full or programmed level, and the description was modified. Table 16 was updated to rename Data to Label and update the type and description. Table 18 was updated to modify the data rate description. Table 19 was updated to modify the type of FIFO empty and FIFO full. FIFO half full was renamed to FIFO half full or programmed level, and its type and description were modified. The "Label Memory Operation" section was added. Information was added to the "Legacy Operation" section to clarify its purpose and configurability. Table 20 was updated to modify the description for receiver 1 data rate, label compare, match ARINC bit 10, match ARINC bit 9, transmitter data rate, and transmitter data rate. Table 21 was updated to change the type from R/W to R for all bits. The signal names cpu_clk and cpu_addr[7:0] were changed to clk and cpu_add[8:0] in Figure 7 through Figure 12. The wave forms were modified in Figure 7, Figure 10, Figure 11, and Figure 12, and notes were added to each figure. Page 1 2 2 3 5 3 5 5 7 8 8-9
10 10 10 11, 12 11
11 12 12 12 13 13 14 15 16-17
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ARINC 429 Bus Interface
v4.0 v3.1
The title of Table 4 was updated. The Fusion device was changed to AFS1500. The "Supported Families" section was updated to include Fusion. The "Core429 Device Requirements" section was updated to include Fusion data.
4 1 3 1 4 9 16 3 3 3 4 4 14
v3.0
The "Core Deliverables" section was updated. Table 5 is new. Table 9 was updated. Figure 9 was updated.
v2.0
The "Core429 Device Requirements" section was updated. Table 1 was updated. Table 2 was updated. Table 3 was updated. Table 4 was updated. Table 20 was updated.
Datasheet Categories
In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as "Product Brief," "Advanced," and "Production." The definitions of these categories are as follows:
Product Brief
The product brief is a summarized version of an advanced or production datasheet containing general product information. This brief summarizes specific device and family information for unreleased products.
Advanced
This datasheet version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production.
Unmarked (production)
This datasheet version contains information that is considered to be final.
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